# Edwin Roger Banks, PhD Thesis 1971
#
# Four-state, five-neighbor CA for universal computation and construction.
# (Appendix IV)
#
# At the top are shown some wires, signals and junctions. These operate
# in a similar fashion to Banks' first three CA. Junctions can act as
# fan-outs and logic gates.
#
# Another type of action is possible here, however. A 'compute' signal
# can be converted to a 'construct' signal which passes down a single-
# cell wire.
#
# Where two construct signals meet, a new arm is constructed to the 
# side. Further construct signal pairs extend the arm further.
#
# Each time an arm is extended further, an echo signal returns. If the
# timing of this echo and the next construct signal pair is correct,
# they trigger the creation of an erasing wing. This travels up the
# arm, deleting it and then depositing a new cell at the end.
#
# Below are shown four examples of erasing wings travelling up
# construction arms and writing new cells at the end. These show that
# any pattern consisting of cells in state 3 ('x') can be constructed.
#
# To activate the new construction, a method is provided to convert
# an erasing wing to a compute signal. It leaves behind some stray cells
# (garbage) but this can be cleaned up if required by writing some new
# cells and then sending a new erasing wing (bottom-most example).
#
# See: http://www.bottomlayer.com/bottom/banks/banks_commentary.htm
# 
x = 93, y = 112, rule = Banks-IV
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